Prior art virtual phase CCD processes are only partially self-aligned. The clocked barrier as well as the virtual barrier are defined by separate masks. This presents a problem of alignment accuracy when the pixel size is reduced. Only the virtual gate P+ region is self aligned to the polysilicon and the virtual well implant is self aligned only at one edge. Both barriers, clocked and virtual are defined by a masking process which has a tolerance limit. This limit becomes a problem when the barriers have submicron dimensions which are necessary for small pixel CCD image sensors. Another problem in the prior art occurs in the virtual barrier region. There is an overlap of the clocked well "As" implant which is compensated by the P+ boron implant to obtain a self aligned edge of the clocked well to the virtual barrier. However, the compensation is not perfect which causes a small retrograde well (parasitic well) in the barrier region. This in turn causes difficulty for charge transfer efficiency, since a small amount of charge can be trapped in this well.